1. Field of the Invention
The present invention relates to an astable oscillator circuit for generating a variable frequency clock signal. More particularly, the invention relates to an oscillator circuit that uses a first, lower frequency oscillator, to modulate and vary the frequency of a second, higher frequency oscillator to generate a variable frequency clock signal. The invention further relates to a method of generating a variable frequency clock signal.
2. Description of Related Art
Various circuits that are designed to generate random data signals use one or more variable frequency clocks as sources of randomness. One example of a variable frequency clock circuit that is used extensively is an astable phase-lock-loop (PLL) circuit. An astable PLL is designed like a conventional PLL, but does not xe2x80x9clockxe2x80x9d onto a particular frequency. Instead, an astable PLL continuously varies in frequency around a central frequency. Astable PLLs are, however, relatively complex and, therefore, increase system costs. Other variable frequency clock circuit designs typically require custom analog circuits to be designed, which also increases system costs.
Hence, there is a need in the art for a variable frequency clock circuit that is simpler than an astable PLL circuit, and that requires no custom analog circuit design.
The present invention relates to a circuit and method for generating a variable frequency clock signal. In one aspect of the present invention, an astable oscillator circuit for generating a clock signal having a variable frequency magnitude includes a first oscillator, a control circuit, and a second oscillator. The first oscillator generates a first signal having a substantially fixed-frequency magnitude. The control circuit is coupled to receive the first signal from the first oscillator an outputs control signals based on the received first signal. The second oscillator is coupled to receive the control signals from the control circuit and generates the variable frequency magnitude clock signal in response to the received control signal.
In another aspect of the invention, a method of generating a clock signal having a variable frequency magnitude includes the step of generating a first signal having a substantially fixed-frequency magnitude. Then, control signals are generated on the basis of the first signal. The variable frequency magnitude clock signal is then generated in response to the control signals.
In still a further aspect of the present invention, an astable oscillator circuit for generating a clock signal having a variable frequency magnitude includes a fixed-frequency oscillation means, a control means, and a variable frequency oscillation means. The fixed-frequency oscillation means generates a substantially fixed-frequency magnitude signal. The control means is coupled to receive the substantially fixed-frequency magnitude signal and generates control signals based at least in part on the substantially fixed-frequency magnitude signal. The variable frequency oscillation means is responsive to the control signals and generates the variable frequency magnitude clock signal.
The present invention provides several advantages over known circuits and methods for providing variable frequency clock signals. First, the present invention is much simpler than various other known designs, such as the astable PLL design. Second, the present invention can be implemented using components from standard cell libraries, without the need for custom-designed circuitry. Third, by using one oscillator to modulate another oscillator, the unpredictability that is inherent in each oscillator circuit is enhanced. And finally, the unpredictability of the overall frequency variation is further enhanced since, not only is the frequency of one oscillator being forced to shift around, but the variations of each oscillator due to manufacturing process deviations, temperature changes, and supply voltage variations are multiplied together.